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IS61LV256

Features: • High-speed access time: 12, 15, 20, 25 ns• Automatic power-down when chip is deselected• CMOS low power operation- 345 mW (max.) operating- 7 mW (max.) CMOS standby• TTL compatible interface levels• Single 3.3V power supply• Fully static operation: n...

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SeekIC No. : 004379151 Detail

IS61LV256: Features: • High-speed access time: 12, 15, 20, 25 ns• Automatic power-down when chip is deselected• CMOS low power operation- 345 mW (max.) operating- 7 mW (max.) CMOS standbyR...

IS61LV256 Data Sheet

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Part Number:
IS61LV256
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• High-speed access time: 12, 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
- 345 mW (max.) operating
- 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh required
• Three-state outputs


Pinout

Connection Diagram Connection Diagram


Specifications

Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect toGND 0.5 to VDD+4.6 V
TSTG Storage Temperature 65 to +125 °C
PT Power Dissipation 65 to +150 W
IOUT DC Output Current (LOW) 20 mA



Description

The ISSI IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns maximum.

When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 mW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil DIP and SOJ, plus the 450-mil TSOP package.




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