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IS65C1024AL

Features: • High-speed access time: 35, 45 ns• Low active power: 100 mW (typical)• Low standby power: 20 W (typical) CMOS standby• Output Enable (OE ) and two Chip Enable (CE1 and CE2) inputs for ease in applications• Fully static operation: no clock or refresh requi...

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SeekIC No. : 004379296 Detail

IS65C1024AL: Features: • High-speed access time: 35, 45 ns• Low active power: 100 mW (typical)• Low standby power: 20 W (typical) CMOS standby• Output Enable (OE ) and two Chip Enable (CE...

IS65C1024AL Data Sheet

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Part Number:
IS65C1024AL
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• High-speed access time: 35, 45 ns
• Low active power: 100 mW (typical)
• Low standby power: 20 W (typical) CMOS standby
• Output Enable (OE ) and two Chip Enable (CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
• Commercial, Industrial, and Automotive temperature ranges available
• Standard Pin Configuration: - 32-pin SOP/ 32-pin TSOP (Type 1)
• Lead free available


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VTERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
TSTG
Storage Temperature
65 to +125
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS  may  cause  permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of  this  specification is
not implied. Exposure to absolute maximum rating  conditions for  extended  periods  may  affect
reliability.


Description

The ISSI IS62C1024AL/IS65C1024AL is a low power, 131,072- word by 8-bit CMOS static RAM. It is fabricated using highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.

When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.

Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory.




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