MFG:LATTICE Package Cooled:N/A D/C:08+
MFG: LATTICE
Package Cooled: N/A
D/C: 08+
Description: The ISPLSI2128Vis a High Density Programmable Logic Device available in 128 and 64 I/O-pin versi...
The ISPLSI2128V is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions. The device contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128V features insystem programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2128V offers nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2128V device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128V device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
Supply Voltage Vcc .................................. -0.5 to +5.6V
Input Voltage Applied ............................. -0.5 to +5.6V
Off-State Output Voltage Applied ........... -0.5 to +5.6V
Storage Temperature ............................ -65 to 150°C
Case Temp. with Power Applied ............ -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
• HIGH DENSITY PROGRAMMABLE LOGIC
- 6000 PLD Gates
- 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
- 128 Registers
- High Speed Global Interconnect
- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
- Interfaces with Standard 5V TTL Devices
- The 128 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2128
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- fmax = 80 MHz Maximum Operating Frequency
- tpd = 10 ns Propagation Delay
- Electrically Erasable and Reprogrammable
- Non-Volatile
- 100% Tested at Time of Manufacture
- Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
- 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
- Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
- Reprogram Soldered Devices for Faster Prototyping
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
- Enhanced Pin Locking Capability
- Three Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Programmable Output Slew Rate Control
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
- Superior Quality of Results
- Tightly Integrated with Leading CAE Vendor Tools
- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
- PC and UNIX Platforms
ISPLSI2128V
PDF/DataSheet Download
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