K4G323222A

Features: • 3.3V power supply• LVTTL compatible with multiplexed address• Dual bank operation• MRS cycle with address key programs-. CAS Latency (2, 3)-. Burst Length (1, 2, 4, 8 & full page)-. Burst Type (Sequential & Interleave)• All inputs are sampled at th...

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K4G323222A Picture
SeekIC No. : 004382755 Detail

K4G323222A: Features: • 3.3V power supply• LVTTL compatible with multiplexed address• Dual bank operation• MRS cycle with address key programs-. CAS Latency (2, 3)-. Burst Length (1, 2, ...

floor Price/Ceiling Price

Part Number:
K4G323222A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Features:

• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual bank operation
• MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst Read Single-bit Write operation
• DQM 0-3 for byte masking
• Auto & self refresh
• 32ms refresh period (2K cycle)
• 100 Pin PQFP, TQFP (14 x 20 mm)




Pinout

  Connection Diagram


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD ,VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 2.0 W
Short circuit current IOS 50 mA

Note :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.




Description

The K4G323222A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 32 bits,fabricated with SAMSUNG¢s high performance CMOS technology.Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.8 columns block write improves performance in graphics systems.




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