K4H1G0438M-LA2

* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe [DQS] (x4,x8)  &  [L(U)DQS] (x16)
* Four banks operation
* Differential clock inputs(CK and CK )
* DLL aligns  DQ and DQS transition with CK transition
* MRS cycle with address key programs -. Read latency  2, 2.5 (clock)  -. Burst length (2, 4, 8)  -. Burst type (sequential & interleave)
* All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
* Data I/O transactions on both edges of data strobe
* Edge aligned data output, center aligned data input
* LDM,UDM for write masking only (x16)
* DM for write masking only (x4, x8)
* Auto & Self refresh
* 7.8us refresh interval(8K/64ms refresh)
* tRFC(Refresh row cycle time) = 120ns
* Maximum burst refresh cycle : 8
* 66pin TSOP II Pb-Free package
* RoHS compliant