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K4S161622H-TC60

Features: • 3.3V power supply• LVTTL compatible with multiplexed address• two banks operation• MRS cycle with address key programs-. CAS Latency ( 2 & 3)-. Burst Length (1, 2, 4, 8 & full page)-. Burst Type (Sequential & Interleave)• All inputs are sampled...

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SeekIC No. : 004382870 Detail

K4S161622H-TC60: Features: • 3.3V power supply• LVTTL compatible with multiplexed address• two banks operation• MRS cycle with address key programs-. CAS Latency ( 2 & 3)-. Burst Length (...

K4S161622H-TC60 Data Sheet

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Part Number:
K4S161622H-TC60
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 3.3V power supply
• LVTTL compatible with multiplexed address
• two banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 32ms refresh period (2K cycle)


Pinout

Connection Diagram


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD ,VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1.0 W
Short circuit current IOS 50 mA

Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.




Description

The K4S161622H-TC60 is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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