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Purchase K4S560432E-UC75, In-stock K4S560432E-UC75 From SeekIC.

MFG:SAMSUNG  Package Cooled:TSOP  D/C:06+  

K4S560432E-UC75 Product Image

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Part Number: K4S560432E-UC75

 

MFG: SAMSUNG

Package Cooled: TSOP

D/C: 06+

Description: The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x16,...


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K4S560432E-UC75 General Description


The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

K4S560432E-UC75 Maximum Ratings

Parameter Short circuit current Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on any pin relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1 W
Short circuit current IOS 50 mA

K4S560432E-UC75 Features

• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs-. CAS latency (2 & 3)-. Burst length (1, 2, 4, 8 & Full page)-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• 54 TSOP(II) Pb-free Package
• RoHS compliant

K4S560432E-UC75 Connection Diagram

K4S560432E-UC75  Connection Diagram

K4S560432E-UC75 datasheet

K4S560432E-UC75
PDF/DataSheet Download

  • Datasheet: K4S560432E-UC75
  • File Size: 203538 KB
  • Manufacturer: SAMSUNG [Samsung semiconductor]
  • Click here to Download

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