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K4Y50164UC

Features: Highest pin bandwidth available- 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling Bi-directional differential RSL(DRSL)- Flexible read/write bandwidth allocation- Minimum pin count On-chip termination- Adaptive impedance matching- Reduced system cost and routing complexity Highest sus...

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SeekIC No. : 004383090 Detail

K4Y50164UC: Features: Highest pin bandwidth available- 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling Bi-directional differential RSL(DRSL)- Flexible read/write bandwidth allocation- Minimum pin count On-c...

K4Y50164UC Data Sheet

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Part Number:
K4Y50164UC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Features:

Highest pin bandwidth available
- 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling
Bi-directional differential RSL(DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
On-chip termination
- Adaptive impedance matching
- Reduced system cost and routing complexity
Highest sustained bandwidth per DRAM device
- Up to 8000 MB/s sustained data rate
- Eight banks : bank-interleaved transaction at full bandwidth
- Dynamic request scheduling
- Early-read-after-write support for maximum efficiency
- Zero overhead refresh
Low Latency
- 2.0/2.5/3.33ns request packets
- Point-to-point data interconnect for fastest possible flight time
- Support for low-latency, fast-cycle cores
Low Power
- 1.8V VDD
- Programmable small-swing I/O signaling(DRSL)
- Low power PLL/DLL design
- Powerdown self-refresh support
- Per pin I/O powerdown for narrow-width operation
0.49us refresh intervals(32K/16ms refresh)
 RoHS compliant


Description

The XDR DRAM device K4Y50164UC is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.

The 512Mb XDR DRAM device K4Y50164UC is a CMOS DRAM organized as 32M words by 16bits. The use of Differential Rambus Signaling Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design technologies.
XDR DRAM devices are capable of sustained data transfers up to 8000 MB/s.

XDR DRAM device K4Y50164UC architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory transactions.

The highly-efficient protocol yields over 95% utilization while allowing fine access granuarity. The K4Y50164UC's eight banks support up
to four interleaved transactions.




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