K5A3x40YT(B)C

NOTES:
1. Minimum DC voltage is -0.3V on Input/ Output balls. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on input / output balls is Vcc+0.3V(Max. 3.6V) which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.
2. Minimum DC voltage is -0.3V on RESET and WP/ACC balls. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on RESETandWP/ACC balls are 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns.
3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The K5A3x40YT(B)C featuring single 3.0V power supply is a Multi Chip Package Memory which combines 32Mbit Dual Bank Flash and 4Mbit fCMOS SRAM.

The 32Mbit Flash memory K5A3x40YT(B)C is organized as 4M x8 or 2M x16 bit and 4Mbit SRAM is organized as 512K x8 or 256K x16 bit. The memory architecture of flash memory is designed to divide its memory arrays into 71 blocks and this provides highly flexible erase and program capability. This device is capable of reading data from one bank while programming or erasing in the other bank with dual bank organization.

The Flash memory K5A3x40YT(B)C performs a program operation in units of 8 bits (Byte) or 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed for typically 0.7sec.

The 4Mbit SRAM K5A3x40YT(B)C supports low data retention voltage for battery backup operation with low data retention current.

The K5A3x40YT(B)C is suitable for the memory of mobile communication system to reduce mount area. This device is available in 69-ball TBGA Type package.