K7J323682M

The K7J323682M and K7J321882M are 37,748,736-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs.They are organized as 1,048,576 words by 36bits for K7J323682M and 2,097,152 words by 18 bits for K7J321882M.

The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports.Memory bandwidth is higher than DDR sram without separate input output as separate read and write ports eliminate bus turn around cycle.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,the data outputs are synchronized to the input clocks ( K and K ).Read data are referenced to echo clock ( CQ or CQ ) outputs.Read address and write address are registered on rising edges of the input K clocks.Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.Synchronous pipeline read and late write enable high speed operations.Simple depth expansion is accomplished by using LD for port selection.Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.Nybble write operation is supported with NW0 and NW1 pins for x8 device.IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7J323682M and K7J321882M are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.