K7M803625B

The K7M803625B and K7M801825B are 9,437,184-bit Synchronous Static SRAMs.

The NtRAMTM, or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles.Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock.Burst order control must be tied "High or Low".Asynchronous inputs include the sleep mode enable(ZZ).Output Enable controls the outputs at any given time.Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.

For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array.

The K7M803625B and K7M801825B are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP and Multiple power and ground pins minimize ground bounce.