K7N401801A

• V_DD=3.3V+0.165V/-0.165V Power Supply.
• V_DDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no datacontention.
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
•  TTL-Level Three-State Outputs.
• 100-TQFP-1420A Package.

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.

The K7N403601A and K7N401801A are 4,718,592 bits Synchronous Static SRAMs.

The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock.Burst order control must be tied "High or Low".Asynchronous inputs include the sleep mode enable(ZZ).Output Enable controls the outputs at any given time.Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incomming signals.

For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock.

The K7N403601A and K7N401801A are implemented with SAMSUNG¢s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce.