Features: • 2.5V ±5% Power Supply.• Byte Writable Function.• Enable clock and suspend operation.• Single READ/WRITE control pin.• Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention .• A interleaved burst or a lin...
K7N803645M: Features: • 2.5V ±5% Power Supply.• Byte Writable Function.• Enable clock and suspend operation.• Single READ/WRITE control pin.• Self-Timed Write Cycle. • Three ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: • 3.3V+0.165V/-0.165V Power Supply.• I/O Supply Voltage 3.3V+0.165V/-0.165V ...
Features: • 2.5V ±5% Power Supply.• Byte Writable Function.• Enable clock and su...
Features: • 3.3V+0.165V/-0.165V Power Supply.• I/O Supply Voltage 3.3V+0.165V/-0.165V ...
• 2.5V ±5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
•100-TQFP-1420A
PARAMETER |
SYMBOL |
RATING |
UNIT |
Voltage on VDD Supply Relative to VSS |
VDD |
-0.3 to 3.6 |
V |
Voltage on Any Other Pin Relative to VSS |
VIN |
-0.3 to 3.6 |
V |
Power Dissipation |
PD |
1.4 |
W |
Storage Temperature |
TSTG |
-65 to 150 |
|
Operating Temperature |
TOPR |
0 to 70 |
|
Storage Temperature Range Under Bias |
TBIAS |
-10 to 85 |
The K7N803645M and K7N801845M are 9,437,184 bits Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory K7N803645M utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low".
K7N803645M Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable K7N803645M controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising edge of the clock input. This K7N803645M feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock.
The K7N803645M and K7N801845M are implemented with SAMSUNG¢s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce.