KK4006B

Features: • Standardized, symmetrial output characteristics• Operating Voltage Range: 3.0 to 18 V• 100% tested for guiescent current at 20 V• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25• Noise margin ( full pa...

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KK4006B Picture
SeekIC No. : 004385592 Detail

KK4006B: Features: • Standardized, symmetrial output characteristics• Operating Voltage Range: 3.0 to 18 V• 100% tested for guiescent current at 20 V• Maximum input current of 1 &micr...

floor Price/Ceiling Price

Part Number:
KK4006B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2025/12/4

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Product Details

Description



Features:

• Standardized, symmetrial output characteristics
• Operating Voltage Range: 3.0 to 18 V
• 100% tested for guiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25
• Noise margin ( full package temperature range):
1.0 V at VDD=5.0 V
2.0 V at VDD =10.0 V
2.5 V at VDD =15.0 V



Pinout

  Connection Diagram


Specifications

Symbol Parameter
Value
Unit
VDD
VIN
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Input Current, per Pin
-0.5 to +20
-0.5 to VDD +0.5
±10
V
V
mA
PD
Ptot
Tstg
Power Dissipation in Still Air, Plastic DIP, SOIC
Package
Power Dissipation per Output Transistor
Storage Temperature
500**

100
-65 to +150
mW

mW
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating: - Plastic DIP from -55 to +100
- SOIC Package from -55 to +65
- Plastic DIP: - 12 mW/ from +100 to +125
- SOIC Package: : - 7 mW/ from +65 to +125



Description

The RCA-4006B types are composed of 4 separate shift register sections: two sections of four stages and two sections of five stages with an output tar at the fourth stage. Each section has an independent single-rail data path.


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