KK74AC651

Features:

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA, 0.1 µA @ 25
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	-0.5 to +7.0	V
VIN	DC Input Voltage (Referenced to GND)	-0.5 to VCC +0.5	V
VOUT	DC Output Voltage (Referenced to GND)	-0.5 to VCC +0.5	V
IIN	DC Input Current, per Pin	±20	mA
IOUT	DC Output Sink/Source Current, per Pin	±50	mA
ICC	DC Supply Current, VCC and GND Pins	±50	mA
PD	Power Dissipation in Still Air, Plastic DIP+                                         SOIC Package+	750 500	mW
TSTG	Storage Temperature	-65 to +150
TL	Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)	260

*Maximum Ratings are those values beyond which damage to the device may occur.
  Functional operation should be restricted to the Recommended Operating Conditions.
  +Derating - Plastic DIP: - 10 mW/ from 65° to 125
             SOIC Package: : - 7 mW/ from 65° to 125



Description

The KK74AC651 is identical in pinout to the LS/ALS651,HC/HCT651. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are comp atible with LS/ALS outputs.

These devices consists of bus transceiver circuits, D-type flip-flop, and control circuitry arranged for multiplex transmission of data directly from the data bus or from the internal storage registers. Direction and Output Enable are provided to select the read-time or stored data function. Data on the A or B Data bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of the select or enable or enable control pins. When A-to-B Source and B-to-A Source are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling Direction and Output Enable. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.
The KK74AC651 has inverted outputs.