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KK74AC74

Features: `Outputs Directly Interface to CMOS, NMOS, and TTL `Operating Voltage Range: 2.0 to 6.0 V `Low Input Current: 1.0 A; 0.1 A @ 25 `High Noise Immunity Characteristic of CMOS Devices `Outputs Source/Sink 24 mAPinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Vol...

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SeekIC No. : 004385738 Detail

KK74AC74: Features: `Outputs Directly Interface to CMOS, NMOS, and TTL `Operating Voltage Range: 2.0 to 6.0 V `Low Input Current: 1.0 A; 0.1 A @ 25 `High Noise Immunity Characteristic of CMOS Devices `Outputs...

KK74AC74 Data Sheet

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Part Number:
KK74AC74
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

`Outputs Directly Interface to CMOS, NMOS, and TTL  
`Operating Voltage Range: 2.0 to 6.0 V  
`Low Input Current: 1.0 A; 0.1 A @ 25   
`High Noise Immunity Characteristic of CMOS Devices  
`Outputs Source/Sink 24 mA 
 


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5to VCC +1.5
V
V OUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5
V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Sink/Source Current, per Pin ±50 mA
ICC DC Supply Current, V and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
                                        SOIC Package+ 		750
500 		mW
Tstg Storage Temperature -65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 		260

*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/ from 65 to 125
SOIC Package: : - 7 mW/ from 65 to 125
 


Description

The KK74AC74 is identical in pinout to the LS/ALS74, HC/HCT74.The device inputs are compatible with standard CMOS ; with pullup resistors, they are compatible with LS/ALS outputs.

This device consists of two D flip-flops with individual Set, Reset, and  Clock  inputs.  Information  at a D-input is sferred to the corresponding Q output on the next positive going edge of the clock input.Both Q and Q outputs are available m each flip-flop. The Set and Reset inputs are asynchronous.




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