KM416S8030B

Features: • JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed address• Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• All ...

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KM416S8030B Picture
SeekIC No. : 004386055 Detail

KM416S8030B: Features: • JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed address• Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3) ...

floor Price/Ceiling Price

Part Number:
KM416S8030B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)



Pinout

  Connection Diagram


Specifications

Parameter
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VIN,VOUT
-1.0 ~ 4.6
V
Voltage on VCC supply relative to VSS
TVCC
-1.0 ~ 4.6
V
Storage Temperature
Tstg
-55 to +150
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOS
50
mA
NOTE:Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
          Functional operation should be restricted to recommended operating condition.
          Exposure to higher than recommended voltage for extended periods of time could affect device reliability.



Description

The KM416S8030B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG¢s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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