KS8695

The KS8695 "Multi-Port Gateway-on-a-Chip" delivers a new level of networking integration and performance for speeding broadband gateway development. The key components integrated in the KS8695 include:

• Integrated layer-2 managed switch with five Fast Ethernet transceivers and patented mixed-signal low-power technology; five MAC units; a high-speed non-blocking switch fabric; a dedicated address lookup engine; an on-chip frame buffer memory and LED controls. One port is partitioned for WAN interface with the other 4 ports for LAN access.

• A 185-MIPS ARM 922T processor with memory management unit (MMU) and 8kB I-cache and 8kB D-cache.

• An independent MAC unit supporting MAC or PHY mode MII interface for networking expansion. Block Diagram
• On checksum errors and TCP/UDP/IP packet header checksum generation. The protocol engine applies to the WAN, LAN and EMAC interfaces.

• DMA engines with burst mode support; Tx and Rx FIFOs to streamline the data transfers between WAN and CPU, CPU and LAN, CPU and EMAC.

• Shared programmable 8/16/32-bit data bus and 22-bit address bus with up to 64MB total memory space for SDRAM, ROM, Flash, SRAM and all peripheral devices.

• Other peripheral support logic including GPIO, a watchdog timer, an interrupt controller and a JTAG debugging interface.

Complete hardware & software reference designs are available.

The KS8695 represents a new level of total solution optimized for broadband gateway system development and renders speedy routing performance & connectivity interfaces for value-added networking expansions.