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MFG:KENDIN Package Cooled:QFP
Part Number: KS8995X
MFG: KENDIN
Package Cooled: QFP
Description: The KS8995X is a highly integrated layer-2 QoS switch with optimized BOM (Bill-Of-Materials) cost for ...
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KS8995X
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DataSheet
General Description
KS8995X General Description
The KS8995X is a highly integrated layer-2 QoS switch with optimized BOM (Bill-Of-Materials) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, dual MII interface for BOM cost reduction, programmable rate limiting to offload CPU tasks, software & hardware power-down , MDC/MDIO control interface and port monitoring to effectively address both current and emerging Fast Ethernet applications.
patented mixed-signal low-power technology, five MAC (Media Access Control) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory.
All PHY units support 10Base-T and 100BaseTX.
In addition, two of the PHY units support 100BaseFX (Ports 4 & 5).
KS8995X Features
• Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard
• Shared memory based switch fabric with fully nonblocking configuration
• 10BaseT, 100BaseTX and 100BaseFX modes (FX in Ports 4 & 5)
• Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII)
• VLAN ID tag/untag options, per-port basis
• Programmable rate limiting, ingress and egress port, rate options for high and low priority, per port basis
• Flow control or drop packet rate limiting (ingress port)
• Broadcast storm protection with % controlglobal and per-port basis
• Optimization for fiber-to-copper media conversion
• Full-chip hardware power-down support (register configuration not saved)
• Per-port based software power-save on PHY (idle link detection, register configuration preserved)
• QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based
• 802.1p/q tag insertion or removal on a per port basis (egress)
• Port-based VLAN support
• MDC and MDI/O interface support to access the MII PHY control registers (not all control registers)
• MII local loopback support
• On-chip 64kB memory for frame buffering (not shared with 1K unicast address table)
• 1.4Gbps high performance memory bandwidth
• Wire speed reception and transmission
• Integrated look-up engine with dedicated 1K unicast MAC addresses
• Automatic address learning, address aging and address migration
• Full duplex IEEE 802.3x and half-duplex back pressure flow control
• Comprehensive LED support
• 7-wire SNI support for legacy MAC interface
• Automatic MDI/MDI-X crossover for plug-and-play
• Low power, 1.8/2.5/3.3V, 0.18um CMOS technology
• Available in 128-pin PQFP package
• Shared memory based switch fabric with fully nonblocking configuration
• 10BaseT, 100BaseTX and 100BaseFX modes (FX in Ports 4 & 5)
• Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII)
• VLAN ID tag/untag options, per-port basis
• Programmable rate limiting, ingress and egress port, rate options for high and low priority, per port basis
• Flow control or drop packet rate limiting (ingress port)
• Broadcast storm protection with % controlglobal and per-port basis
• Optimization for fiber-to-copper media conversion
• Full-chip hardware power-down support (register configuration not saved)
• Per-port based software power-save on PHY (idle link detection, register configuration preserved)
• QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based
• 802.1p/q tag insertion or removal on a per port basis (egress)
• Port-based VLAN support
• MDC and MDI/O interface support to access the MII PHY control registers (not all control registers)
• MII local loopback support
• On-chip 64kB memory for frame buffering (not shared with 1K unicast address table)
• 1.4Gbps high performance memory bandwidth
• Wire speed reception and transmission
• Integrated look-up engine with dedicated 1K unicast MAC addresses
• Automatic address learning, address aging and address migration
• Full duplex IEEE 802.3x and half-duplex back pressure flow control
• Comprehensive LED support
• 7-wire SNI support for legacy MAC interface
• Automatic MDI/MDI-X crossover for plug-and-play
• Low power, 1.8/2.5/3.3V, 0.18um CMOS technology
• Available in 128-pin PQFP package
KS8995X Typical Application
• Broadband gateway/firewall/VPN
• Integrated DSL or cable modem multi-port router
• Wireless LAN access point + gateway
• Home networking expansion
• Standalone 10/100 switch
• Hotel/campus/MxU gateway
• Enterprise VoIP gateway/phone
• FTTx customer premise equipment
• Media converter
• Integrated DSL or cable modem multi-port router
• Wireless LAN access point + gateway
• Home networking expansion
• Standalone 10/100 switch
• Hotel/campus/MxU gateway
• Enterprise VoIP gateway/phone
• FTTx customer premise equipment
• Media converter
KS8995X
PDF/DataSheet Download
- Datasheet: KS8995X
- File Size: 31172 KB
- Manufacturer: MICREL [Micrel Semiconductor]
- Click here to Download
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