L29C525

The L29C525 is a high-speed, low power CMOS pipeline register.  It is pin-for-pin compatible with the AMD Am29525.  The L29C525 can be configured as two independent 8-level pipelines or as a single 16-level pipeline.  The configuration imple- men ted is determined by the instruc- tion code (I1-0) as shown in Table 2. 

The I internal routing of data and l oading of each register.  For instruction I 1-0 = 00 (Push A and B), data  applied at the D7-0 inputs is latched into register A0 on the rising edge of CLK.  The contents of A0 simultaneously move to register A1, A1 moves to A2, and so on.  The contents of register A7 are wrapped back to register B0.  The registers on the B side are similarly shifted, with the contents of register B7 lost.

Instruction I1-0 = 01 (Push B) acts similarly to the Push A and B instruction, except that only the B side registers are shifted.  The input data is applied to register B0, and the contents of register B7 are lost.  The contents of the A side registers are unaffected.  Instruction I1-0 = 10 (Push A) is identical to the Push B  instruction, except that the A side  registers are shifted and the B side registers are unaffected.


Instruction I1-0 = 11 (Hold) causes no internal data movement.  It is equiva- lent to preventing the application of a clock edge to any internal register.

The contents of any of the registers is selectable at the output through the use of the S3-0 control inputs.  The in dependence of the I and S control lines allows simultaneous reading and writing.  Encoding for the S3-0 controls is given in Table 3.