LF43168

•  66 MHz Data and Computation Rate
•  Two Independent 8-Tap or Single 16-Tap FIR Filters
•  10-bit Data and Coefficient Inputs
•  32 Programmable Coefficient Sets
•  Supports Interleaved Coefficient Sets
•  User Programmable Decimation up to 16:1
•  Maximum of 256 FIR Filter Taps, 16 x 16 2-D Kernels, or 10 x 20-bit Data and Coefficients
•  Replaces Harris HSP43168
•  Package Styles Available:
    • 84-pin Plastic LCC, J-Lead
    • 100-pin Plastic Quad Flatpack

Storage temperature .............................................................65 to +150
Operating ambient temperature .......................................55 to +125VCC
supply voltage with respect to ground ....................................0.5 V to +7.0 V
Input signal with respect to ground ................................0.5 V to V_CC + 0.5 V
Signal applied to high impedance output .........................0.5 V to V_CC + 0.5 V
Output current into low outputs ................................................................25 mA
Latchup current ......................................................................................> 400 mA

The LF43168 is a high-speed dual FIR filter capable of filtering data at realtime video rates. The LF43168 contains two FIR filters which may be used as two separate filters or cascaded to form one filter. The input and coefficient data are both 10-bits and can be in unsigned, two's complement, or mixed mode format.

The filter architecture is optimized for symmetric coefficient sets. When symmetric coefficient sets are used, each filter can be configured as an 8-tap FIR filter. If the two filters are cascaded, a 16-tap FIR filter can be implemented. When asymmetric coefficient sets are used, each filter is configured as a 4-tap FIR filter. If both filters are cascaded, an 8-tap filter canbe implemented. The LF43168 can decimate the output data by as much as 16:1. When the device is programmed to decimate, the number of clock cycles available to calculate filter taps increases. When configured for 16:1 decimation, each filter can be configured as a 128-tap FIR filter (if symmetric coefficient sets are used). By cascading these two filters, the device can be configured as a 256-tap FIR filter.

There is on-chip storage for 32 different sets of coefficients. Each set consists of eight coefficients. Access to more than one coefficient set facilitates adaptive filtering operations. The 28-bit filter output can be rounded from 8 to 19 bits.