LH28F800BGH-L

• SmartVoltage technology
    2.7 V, 3.3 V or 5 V VCC
    2.7 V, 3.3 V, 5 V or 12 V VPP
• High performance read access time
LH28F800BG-L85/BGH-L85
    85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
LH28F800BG-L12/BGH-L12
    120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/150 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
    Word write suspend to read
    Block erase suspend to word write
   Block erase suspend to read
• Enhanced data protection features
    Absolute protection with V_PP = GND
   Block erase/word write lockout during power transitions
   Boot blocks protection with WP# = VIL
• SRAM-compatible write interface
• Optimized array blocking architecture
    Two 4 k-word boot blocks
    Six 4 k-word parameter blocks
    Fifteen 32 k-word main blocks
    Top or bottom boot location
• Enhanced cycling capability
   100 000 block erase cycles
• Low power management
    Deep power-down mode
    Automatic power saving mode decreases I_CC in static mode
• Automated word write and block erase
    Command user interface
    Status register
• ETOX^TM* V nonvolatile flash technology
• Packages
    48-pin TSOP Type I (TSOP048-P-1220)
Normal bend/Reverse bend
    48-ball CSP (FBGA048-P-0808)