Features: `20 ns Multiply-Accumulate Time
`Replaces Fairchild TMC2210, Cypress CY7C510, IDT 7210L, and AMD Am29510
`Two's Complement or Unsigned Operands
` Accumulator Performs Preload, Accumulate, and Subtract
`Three-State Outputs
`68-pin PLCC, J-Lead
SpecificationsStorage temperature .................................................. 65 to +150
Operating ambient temperature ................................. 55 to +125
VCC supply voltage with respect to ground ................ 0.5 V to +7.0 V
Input signal with respect to ground ............................ 3.0 V to +7.0 V
Signal applied to high impedance output .................... 3.0 V to +7.0 V
Output current into low outputs .................................................. 25 mA
Latchup current ...................................................................... > 400 mADescriptionThe LMA1010/2010 are high-speed, low power 16-bit multiplier-accumulators.
The LMA1010/2010 are functionally identical; they differ only in packaging. Full military ambient temperature range operation is achieved with advanced CMOS technology.
The LMA1010/2010 produce the 32-bit product of two 16-bit numbers.
The results of a series of multiplications may be accumulated to form the sum of products. Accumulation is performed to 35-bit precision with the multiplier product sign extended as appropriate. Data present at the A and B input registers is latched on the rising edges of CLK A and CLK B respectively. RND, TC, ACC, and SUB controls are latched on the rising edge of the logical OR of CLK A and CLK B. TC specifies the input as two's complement (TC HIGH) or unsigned magnitude (TC LOW). RND, when HIGH, adds '1' to the most significant bit position of the least significant half of the product. Subsequent truncation of the 16 least significant bits produces a result correctly rounded to 16-bit precision. ACC and SUB control accumulator operation. ACC HIGH results in addition of the multiplier product and the accumulator contents, with the result stored in the accumulator register on the rising edge of CLK R. ACC and SUB HIGH results in subtraction of the accumulator contents from the multiplier product, with the result stored in the accumulator register. With ACC LOW and SUB LOW, no accumulation occurs and the next product is loaded directly into the accumulator register. ACC LOW and SUB HIGH is undefined.
The LMA1010/2010 output register (accumulator register) is divided into three independently controlled sections.
The least significant result (LSR) and most significant result (MSR) registers are 16 bits in length.
The extended result register (XTR) is 3 bits long.
The output signals R15-0 and input signals B15-0 share the same bidirectional pins.Each output register has an independent output enable control. In addition to providing three-state control of the output buffers, when OEX, OEM, or OEL are HIGH and PREL is HIGH, data can be preloaded via the bidirectional output pins into the respective output registers. Data present on the output pins is latched on the rising edge of CLK R.
The interrelation of PREL and the enable controls is summarized in Table 1.
LMA1010/2010 Data Sheet
