LMU12

•25 ns Worst-Case Multiply Time
• Low Power CMOS Technology
• Replaces Fairchild MPY112K
•Two's Complement or Unsigned Operands
•Three-State Outputs
• Package Styles Available:
• 48-pin PDIP
• 52-pin PLCC, J-Lead

The LMU12 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology.

The LMU12 is pin and functionally compatible with Fairchilds's MPY112K.

The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B). Two's complement or unsigned magnitude operands are accommodated via the operand control bit (TC) which is loaded along with the B operands.

The operands are specified to be in two's complement format when TC is asserted and unsigned magnitude when TC is deasserted. Mixed mode operation is not allowed. For two's complement operands, the 17 most significant bits at the output of the asynchronous multiplier array are shifted one bit position to the left.

This is done to discard the redundant copy of the sign-bit, which is in the most significant bit position, and extend the bit precision by one bit.

The result is then truncated to the 16 MSB's and loaded into the output register on the rising edge of CLK B.

The contents of the output register are made available via three-state buffers by asserting OE. When OE is deasserted, the outputs (R23-8) are in the high impedance state.