LP5550

Features:

· Supports high-efficiency PowerWise Technology Adaptive Voltage Scaling
· PWI open standard interface for system power management
· Digitally controlled intelligent voltage scaling
· 1 MHz PWM switching frequency
·Auto or PWI controlled PFM mode transition
· Internal soft start/startup sequencing.
· 3 programmable LDOs for I/O, PLL, and memory retention supply generation.
·Power OK output.




Application

· GSM/GPRS/EDGE & UMTS cellular handsets
· Hand-held radios
·PDAs
· Battery powered devices
· Portable instruments




Specifications

Input Min Voltage	3 Volt
Input Max Voltage	5.5 Volt
Output Range	Buck: 0.6 to 1.2V; LDO1: 0.7 to 2.2V; LDO2: 1.5 to 3.3V; LDO3: 0.6 to 1.35V
Channels	4 Channels
Dropout Voltage	0.26 Volt
PowerWise Technology	Adaptive Voltage Scaling
Output1 VoutMin	0.6 Volt
Output1 VoutMax	1.2 Volt
Output1 IoutMax	300 mA
Output1 Topology	Buck
Output2 VoutMin	0.7 Volt
Output2 VoutMax	2.2 Volt
Output2 IoutMax	100 mA
Output2 Topology	LDO
Output3 VoutMin	1.5
Output3 VoutMax	3.3 Volt
Output3 IoutMax	250 mA
Output3 Topology	LDO
Output4 VoutMin	0.6 Volt
Output4 VoutMax	1.35 Volt
Output4 IoutMax	50 mA
Output4 Topology	LDO
Special Features	PowerWise 1.0 compliant. 1 AVS Buck, 3 LDOs.
Topology	Buck, LDO
Switching Frequency	1000 kHz
Adj Switch Frequency	No
Sync Pin	No
RegType	Power Management Unit
Step-Down	Yes
Step-Up	No
Inverting	No
Flyback	No
Efficiency (peak)	90 %
Adjustable Output	Yes
Error Flag	No
On/Off Pin	Yes
Multiple Output Capability	Yes
Temperature Min	-40 deg C
Temperature Max	+125 deg C
PowerWise	Yes
View Using Catalog

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VBAT1, VBAT2, VBATSW -0.3 to +6.0V
VO1, VO2, VO3 to GND -0.3 to +VBAT1+0.3V
ENABLE, RESETN, VFB,
SW,
SPWI, SCLK, PWROK -0.3 to VBAT2+0.3V
DGND, AGND, SWGND to
GND SLUG
±0.3V
Junction Temperature
(TJ-MAX)
150
Storage Temperature Range -65 to 150
Maximum Continuous
Power Dissipation
(PD-MAX) (Note 3)
1.0 W
Maximum Lead
Temperature (Soldering)
Note 4
ESD Rating (Note 3)
Human Body Model:
SW pin 1.0kV
All other pins 2.0kV




Description

The LP5550 is a PWI 1.0 compliant Energy Management System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications processors.

The LP5550 contains an advanced, digitally controlled switching regulator for supplying variable voltage to processor core and memory. The device also incorporates 3 programmable LDO-regulators for powering I/O, PLLs and maintaining memory retention in shutdown-mode.

The device is controlled via the PWI open-standard interface. The LP5550 operates cooperatively with PowerWise technology compatible processors to optimize supply voltages adaptively over process and temperature variations or dynamically using frequency/voltage pre-characterized look-up tables.

Reliability Metrics

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Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LP5550SQ	CMOS7	0	16561	0	0	954000	4	270700104
LP5550SQX	CMOS7	0	16561	0	0	954000	4	270700104

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

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Title	Size in Kbytes	Date
PowerWise(R) Evaluation Kit Ordering Information			View
Processor Energy Savings Through Adaptive Voltage Scaling			View

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Application Notes

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Title	Size in Kbytes	Date
AN-1460: Application Note 1460 Emulating the PowerWise Interface Using GPIOs and Software	448 Kbytes	12-Apr-06	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes

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Title	Size in Kbytes	Date
AN-1653: Application Note 1653 User's Graphical User Interface(GUI) for LP555x Evaluation Board PowerWise? Technology Compliant Energy Management Unit	1675 Kbytes	7-Jun-07	Download
AN-1857: Application Note 1857 LP5553 Evaluation Kit	3940 Kbytes	25-Mar-09	Download
AN-1610: Application Note 1610 LP5552 Evaluation Board	10829 Kbytes	20-May-08	Download
AN-1467: Application Note 1467 LP5551 Evaluation Board	32843 Kbytes	8-Jun-07	Download
AN-1467 (Japanese): Application Note 1467 LP5551 Evaluation Board 640){this.height=this.height*640/this.width;this.width=640;}' border="0" alt=" Connection Diagram">	1847 Kbytes

If you have trouble printing or viewing PDF file(s), see Printing Problems.

·The LP5550 is a PWI 1.0 compliant Energy Management System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications processors.

·The LP5550 contains an advanced, digitally controlled switching regulator for supplying variable voltage to processor core and memory. The device also incorporates 3 programmable LDO-regulators for powering I/O, PLLs and maintaining memory retention in shutdown-mode.

·The device is controlled via the PWI open-standard interface.

·The LP5550 operates cooperatively with PowerWise technology compatible processors to optimize supply voltages adaptively over process and temperature variations or dynamically using frequency/voltage pre-characterized look-up tables.