LP61L1008

Features: · Single 3.3V ± 10% power supply· Access times: 12/15 ns (max.)· Current: Operating: 180mA (max.) Standby: 5mA (max.)· Full static operation, no clock or refreshing required· All inputs and outputs are directly TTL compatible· Center Power/Ground Pin Configuration· Common I/O using three...

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LP61L1008 Picture
SeekIC No. : 004398974 Detail

LP61L1008: Features: · Single 3.3V ± 10% power supply· Access times: 12/15 ns (max.)· Current: Operating: 180mA (max.) Standby: 5mA (max.)· Full static operation, no clock or refreshing required· All inputs an...

floor Price/Ceiling Price

Part Number:
LP61L1008
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/26

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Product Details

Description



Features:

· Single 3.3V ± 10% power supply
· Access times: 12/15 ns (max.)
· Current: Operating: 180mA (max.) Standby: 5mA (max.)
· Full static operation, no clock or refreshing required
· All inputs and outputs are directly TTL compatible
· Center Power/Ground Pin Configuration
· Common I/O using three-state output
· Output enable and two chip enable inputs for easy application
· Data retention voltage: 2.0V (min.)
· Available in 32-pin SOJ 300 mil and 32-pin sTSOP packages



Pinout

  Connection Diagram


Specifications

VCC to GND .............................................. -0.5V to +4.6V
IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V
Operating Temperature, Topr ...................... 0 to +70
Storage Temperature, Tstg..................... -55 to +125
Temperature Under Bias, Tbias................ -10 to +85
Power Dissipation, Pt................................................1.0W
Soldering Temp. & Time .............................260°C, 10 sec



Description

The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply.

Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

The chip enable input is provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing.

Data retention is guaranteed at a power supply voltage as low as 2.0V.


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