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Part Number: M1040
Description: The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock p...
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M1040
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General Description
M1040 General Description
The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. This device provides two outputs. External loop components allow the tailoring of PLL loop response.
M1040 Maximum Ratings
|
Symbol |
Parameter |
Rating |
Unit |
|
VI |
Inputs |
-0.5 to VCC +0.5 |
V |
|
VO |
Outputs |
-0.5 to VCC +0.5 |
V |
|
VCC |
Power Supply Voltage |
4.6 |
V |
|
TS |
Storage Temperature |
-45 to +100 |
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
M1040 Features
· Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz)
· Output frequencies of 62.5 to 175 MHz *; Two differential LVPECL outputs (CML, LVDS options available)
· Loss of Lock (LOL) indicator output
· Narrow Bandwidth control input (NBW pin); Initialization (INIT) input overrides NBW at power-up
· Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL
· AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure; Hitless Switching (HS), Phase Build-out (PBO) options enable SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
· Acknowledge pin (REF_ACK pin) indicates the actively selected reference input
· Industrial temperature available
· Single 3.3V power supply
· Small 9 x 9 mm SMT (surface mount) package
· Output frequencies of 62.5 to 175 MHz *; Two differential LVPECL outputs (CML, LVDS options available)
· Loss of Lock (LOL) indicator output
· Narrow Bandwidth control input (NBW pin); Initialization (INIT) input overrides NBW at power-up
· Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL
· AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure; Hitless Switching (HS), Phase Build-out (PBO) options enable SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
· Acknowledge pin (REF_ACK pin) indicates the actively selected reference input
· Industrial temperature available
· Single 3.3V power supply
· Small 9 x 9 mm SMT (surface mount) package
M1040 Connection Diagram
M1040
PDF/DataSheet Download
- Datasheet: M1040
- File Size: 447062 KB
- Manufacturer: ICST [Integrated Circuit Systems]
- Click here to Download
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