Purchase M12S16161A, In-stock M12S16161A From SeekIC.
Part Number: M12S16161A
Description: The M12S16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 word...
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M12S16161A
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DataSheet
General Description
M12S16161A General Description
The M12S16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
M12S16161A Maximum Ratings
|
Parameter |
Symbol |
Value |
Unit |
| Voltage on any pin relative to VSS |
VIN,VOUT |
-1.0 ~ 4.6 |
V |
| Voltage on VDD supply relative to VSS |
VDD,VDDQ |
-1.0 ~ 4.6 |
V |
| Storage temperature |
TSTG |
-55 ~ + 150 |
|
| Power dissipation |
PD |
0.7 |
W |
| Short circuit current |
IOS |
50 |
MA |
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
M12S16161A Features
· 2.5V power supply
· LVCMOS compatible with multiplexed address
· Dual banks operation
· MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
· EMRS cycle with address key programs.
· All inputs are sampled at the positive going edge of the system clock
· Burst Read Single-bit Write operation
· Special Function Support.
- PASR (Partial Array Self Refresh )
- TCSR (Temperature compensated Self Refresh)
- DS (Driver Strength)
· DQM for masking
· Auto & self refresh
·32ms refresh period (2K cycle)
· LVCMOS compatible with multiplexed address
· Dual banks operation
· MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
· EMRS cycle with address key programs.
· All inputs are sampled at the positive going edge of the system clock
· Burst Read Single-bit Write operation
· Special Function Support.
- PASR (Partial Array Self Refresh )
- TCSR (Temperature compensated Self Refresh)
- DS (Driver Strength)
· DQM for masking
· Auto & self refresh
·32ms refresh period (2K cycle)
M12S16161A Connection Diagram
M12S16161A
PDF/DataSheet Download
- Datasheet: M12S16161A
- File Size: 892692 KB
- Manufacturer: ETC [ETC]
- Click here to Download
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- ·M12L16161A-4.3T
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- ·M12L16161A-5T
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