M24128-BR

These I²C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32K x 8 bits (M24256-BW and M24256- BR) and 16K x 8 bits (M24128-BW and M24128- BR).

I²C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus definition. The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Writeoperations are initiated by a Start condition, generated by the bus mastermaster. The Start condition is followed by a Device Select Code and R ead/Write bit (RW) (as described in Table 3.), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Power On Reset
In order to prevent inadvertent Write operations during Power Up, a Power On Reset (POR) circuit is implemented. 

At Power Up, the device will not respond to any instruction until VCC has reached the POR threshold voltage (this threshold is lower than the VCC minimum operating voltage defined in Table 8. and Table 9.). In the same way, as soon as VCC drops from the normal operating voltage, below the POR threshold voltage, all the operations are disabled and the device will not respond to any instruction. Prior to selecting and issuing instructions to the memory, a valid and stable VCC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t_W).