M24512

These I²C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 64K x 8 bits.

I²C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus definition. The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master master. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as described in Table 3.), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Power On Reset

In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up, the device will not respond to any command until V_CC has reached the Power On Reset threshold voltage (this threshold is lower than the _VCC min operating voltage defined in Tables 8 and 9). In the same way, as soon as V_CC drops from the normal operating voltage, below the Power On Reset threshold voltage, the device stops to respond to any command.

Prior to selecting and issuing commands to the memory, a valid and stable V_CC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the command and, for a Write instruction, until the completion of the internal write cycle (t_W).