M28W160ECB

SUMMARY DESCRIPTION The M28W160EC is a 16 Mbit (1 Mbit x 16) nonvolatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply.

VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features an asymmetrical blocked architecture.

The M28W160EC has an array of 39 blocks: 8 Parameter Blocks of 4 KWord and 31 Main Blocks of 32 KWord. M28W160ECT has the Parameter Blocks at the top of the memory address space while the M28W160ECB locates the Parameter Blocks starting from the bottom.

The memory maps are shown in Figure 5., Block Addresses. The M28W160EC features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure.

There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at powerup. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed.

Each block can be programmed and erased over 100,000 cycles. The device includes a 128 bit Protection Register and a Security Block to increase the protection of a system design. The Protection Register is divided into two 64 bit segments, the first one contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 6., shows the Security Block and Protection Register Memory Map. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The memory is offered in TSOP48 (10 X 20mm) and TFBGA46 (6.39 x 6.37mm, 0.75mm pitch) packages. and is supplied with all the bits erased (set to '1'). In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes.