Purchase M2V56S20TP, In-stock M2V56S20TP From SeekIC.
Part Number: M2V56S20TP
Description: M2V56S20TP is a 4-bank x 16777216-word x 4-bit, 2V56S30TP is a 4-bank x 8388608-word x 8-bit, 2V56S40T...
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M2V56S20TP
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DataSheet
General Description
M2V56S20TP General Description
M2V56S20TP is a 4-bank x 16777216-word x 4-bit, 2V56S30TP is a 4-bank x 8388608-word x 8-bit, 2V56S40TP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz (-7/-8) , 133MHz (-6), and are suitable for main memory or graphic memory in computer systems.
M2V56S20TP Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
| Vdd | Supply Voltage |
with respect to Vss |
-0.5 ~ 4.6 |
V |
| VddQ | Supply Voltage for Output |
with respect to VssQ |
-0.5 ~ 4.6 |
V |
| VI | Input Voltage |
with respect to Vss |
-0.5 ~ Vdd+0.5 |
V |
| VO | Output Voltage |
with respect to VssQ |
-0.5~ VddQ+0.5 |
V |
| IO | Output Current |
50 |
mA | |
| Pd | Power Dissipation |
Ta = 25 |
1000 |
mW |
| Topr | Operating Temperature |
0 ~ 70 |
||
| Tstg | Storage Temperature |
-65 ~ 150 |
M2V56S20TP Features
· Single 3.3v±0.3V power supply
· Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)
· Fully Synchronous operation referenced to clock rising edge
· Single Data Rate
· 4 bank operation controlled by BA0, BA1 (Bank Address)
· /CAS latency- 2/3 (programmable)
· Burst length- 1/2/4/8/full page (programmable)
· Burst type- sequential / interleave (programmable)
· Random column access
· Auto precharge / All bank precharge controlled by A10
· 8192 refresh cycles /64ms (4 banks concurrent refresh)
· Auto refresh and Self refresh
· Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
· LVTTL Interface
· 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
· Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)
· Fully Synchronous operation referenced to clock rising edge
· Single Data Rate
· 4 bank operation controlled by BA0, BA1 (Bank Address)
· /CAS latency- 2/3 (programmable)
· Burst length- 1/2/4/8/full page (programmable)
· Burst type- sequential / interleave (programmable)
· Random column access
· Auto precharge / All bank precharge controlled by A10
· 8192 refresh cycles /64ms (4 banks concurrent refresh)
· Auto refresh and Self refresh
· Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
· LVTTL Interface
· 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M2V56S20TP Connection Diagram
M2V56S20TP
PDF/DataSheet Download
- Datasheet: M2V56S20TP
- File Size: 249960 KB
- Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
- Click here to Download
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- ·M2V12D30TP
- MITSUBISHI [Mitsubishi Electric Semiconductor]
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- ·M2V12D30TP-10
- MITSUBISHI [Mitsubishi Electric Semiconductor]
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- ·M2V12D30TP-10L
- MITSUBISHI [Mitsubishi Electric Semiconductor]
- 512M Double Data Rate Synchronous DRAM
- 772135 KB
M2V56S20TP Relative Products
M2V56S20ATP
M2V56S20ATP is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V...
M2V56S20AKT
M2V56S20AKT is a 4-bank x 16777216-word x 4-bit, 2V56S30AKT is a 4-bank x 8388608-word x 8-bit, 2V56S40AKT is a 4-bank x 4194304-word x 16-bit, ynchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of LK. The M2V56S2...
M2V28S40TP
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are refere...
M2V28S40ATP
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are ref...
M2V28S30TP
M2V28S30TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are refere...
M2V28S30ATP
M2V28S30ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are ref...
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