Purchase M2V64S40DTP, In-stock M2V64S40DTP From SeekIC.
Part Number: M2V64S40DTP
Description: M2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M2...
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M2V64S40DTP
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DataSheet
General Description
M2V64S40DTP General Description
M2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20DTP, M2V64S30DTP and M2V64S40DTP achieve very high speed data rate up to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
M2V64S40DTP Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
| Vdd | Supply Voltage |
with respect to Vss |
-0.5 ~ 4.6 |
V |
| VddQ | Supply Voltage for Output |
with respect to VssQ |
-0.5 ~ 4.6 |
V |
| VI | Input Voltage |
with respect to Vss |
-0.5 ~ Vdd+0.5 |
V |
| VO | Output Voltage |
with respect to VssQ |
-0.5~ VddQ+0.5 |
V |
| IO | Output Current |
50 |
mA | |
| Pd | Power Dissipation |
Ta = 25 |
1000 |
mW |
| Topr | Operating Temperature |
0 ~ 70 |
||
| Tstg | Storage Temperature |
-65 ~ 150 |
M2V64S40DTP Features
· Single 3.3v±0.3V power supply
· Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>
· Fully Synchronous operation referenced to clock rising edge
· 4 bank operation controlled by BA0 & BA1 (Bank Address)
· /CAS latency- 2 and 3 (programmable)
· Burst length- 1, 2, 4, 8 and full page (programmable)
· Burst type- sequential and interleave (programmable)
· Byte Control- DQML and DQMU for M2V64S40DTP
· Random column access
· Auto precharge and All bank precharge controlled by A10
· Auto refresh and Self refresh
· 4096 refresh cycles every 64ms
· LVTTL Interface
· 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
· Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>
· Fully Synchronous operation referenced to clock rising edge
· 4 bank operation controlled by BA0 & BA1 (Bank Address)
· /CAS latency- 2 and 3 (programmable)
· Burst length- 1, 2, 4, 8 and full page (programmable)
· Burst type- sequential and interleave (programmable)
· Byte Control- DQML and DQMU for M2V64S40DTP
· Random column access
· Auto precharge and All bank precharge controlled by A10
· Auto refresh and Self refresh
· 4096 refresh cycles every 64ms
· LVTTL Interface
· 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M2V64S40DTP Connection Diagram
M2V64S40DTP
PDF/DataSheet Download
- Datasheet: M2V64S40DTP
- File Size: 438013 KB
- Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
- Click here to Download
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M2V64S40DTP Relative Products
M2V64S40BTP
The M2V64S40BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referen...
M2V64S30DTP
M2V64S30DTP is a 4-bank x 4,194,304-word x 4-bit, M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2...
M2V64S30BTP
The M2V64S30BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referen...
M2V64S20DTP
M2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2...
M2V64S20BTP
The M2V64S20BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referen...
M2V56S40TP-6
M2V56S40TP-6 is a 4-bank x 16777216-word x 4-bit, M2V56S30TP is a 4-bank x 8388608-word x 8-bit, M2V56S40TP-6 is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2...
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