M37640E8-XXXF

An on-chip oscillator provides the system and peripheral clocks as well as the USB clock necessary for operation. This oscillator circuit is comprised of amplifiers that provide the gain necessary for oscillation, oscillation control logic, a frequency synthesizer, and buffering of the clock signals. A flow diagram for the oscillator circuit is shown in Figure 2-6 and a block diagram of the oscillator circuit is shown in Figure 2-7. The following external clock inputs are supported:
   • A quartz crystal oscillator of up to 24 MHz, connected to the X_in and Xout pins.
   • An external clock signal of up to 48 MHz, connected to the X_in pin.
   • A ceramic resonator or quartz crystal oscillator of 32.768 kHz, connected to the XC_in and XC_out pins.
   • An external clock signal of up to 5.12 MHz, connected to the XC_in pin.

The frequency synthesizer can be used to generate a 48MHz clock signal (fUSB) needed by the USB block and clock fSYN, which can be chosen as the source for the system and peripheral clocks. Both fUSB and fSYN are phase-locked frequency multiples of the frequency synthesizer input. The inputs to the frequency synthesizer can be either X_in or XC_in.

The two-phase non-overlapping system clock (CPU and peripherals) is derived from the source to the clock circuit and is 1/2 the frequency of the source. (i.e. Source = 24 MHz, system clock = 12 MHz) Any one of four clock signals can be chosen as the source for the system and peripheral clocks; fX_in/ 2, fX_in, fXC_in, or fSYN. The selection is based on the values of bits CPMA6, CPMA7 and CCR7. The default source after reset is fX_in/2.

The default source for the system and peripheral clocks is fX_in/2. If fX_in = 24MHz, then the CPU will be running at F = 6MHz (low frequency mode. For the CPU to run in high frequency mode, i.e., source of clock = fX_in, write a "1" to bit 7 of the clock control register.

The drive strength of the X_out and XC_out inverting amplifier can be controlled by bits CPMB7 and CPMA3, respectively. High drive is the default at reset or after executing a STP instruction and must be chosen whenever restarting X_in or XC_in oscillation if a ceramic or crystal oscillator is used. When oscillation has been established, low drive can be selected to reduce power consumption. If an external clock signal is input to X_in or XC_in, the inverting amplifiers can be disabled by means of the CCR6 and CCR7 bits, respectively, in order to reduce power consumption.