M48T129Y

The M48T129Y/V TIMEKEEPER RAM is a 128Kb x 8 non-volatile static RAM and real time clock, with programmable alarms and a watchdog timer. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. The M48T129Y/V directly replaces industry standard 128Kb x 8 SRAM. It also provides the non-volatility of Flash without any requirement for special write timing or limitations on the number of writes that can be performed.

For surface mount environments ST provides a Chip Set solution consisting of a 44 pin 330mil SOIC TIMEKEEPER Supervisor (M48T201V/Y) and a 32 pin TSOP (8 x 20mm) LPSRAM (M68Z128/W) packages.

The 44 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery.

The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting.The SNAPHAT housing is keyed to prevent reverse insertion.

The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Txx-BR12SH1".

The 32 pin 600 mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single package. Figure 3 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. The nine clock bytes (1FFFFh-1FFF9h and 1FFF1h) are not the actual clock counters, they are memory locations consisting of BiPORT^® read/write memory cells within the static RAM array.

The M48T129Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. Byte 1FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.

Byte 1FFF7h contains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the Watchdog
Steering bit (WDS). Bytes 1FFF6h-1FFF2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 1FFF1h contains century information. Byte 1FFF0h contains additional flag information pertaining to the watchdog timer, the alarm condition and the battery status. The M48T129Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When V_CC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As V_CC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.