M58LW064D

The M58LW064D is a 64 Mbit (8Mb x 8 or 4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7V to 3.6V) core supply.

The memory is divided into 64 blocks of 1Mbit that can be erased independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register.The command set required to control the memory is consistent with JEDEC standards.

The Write Buffer allows the microprocessor to program from 1 to 16 Words in parallel, both speeding up the programming and freeing up the microprocessor to perform other work. A Word Program command is available to program a single word.

Erase can be suspended in order to perform either Read or Program in any other block and then resumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles.

Individual block protection against Program or Erase is provided for data security. All blocks are protected during power-up. The protection of the blocks is non-volatile; after power-up the protection status of each block is restored to the state when power was last removed. Software commands are provided to allow protection of some or all of the blocks and to cancel all block protection bits simultaneously. All Program or Erase operations are blocked when the Program Erase Enable input VPEN is low.

The Reset/Power-Down pin is used to apply a Hardware Reset to the enabled memory and to set the device in power-down mode.

The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: Ready/ Busy mode where a static signal indicates the status of the P/E.C, and Status mode where a pulsing signal indicates the end of a Program or Block Erase operation. In Status mode it can be used as a system interrupt signal, useful for saving CPU time.

The Bus operations of the device are controlled by Output Enable, Write Enable and three different Chip Enables.n Refer to Table 2, Device Enable, for all possible combinations to enable and disable the device. Together they allow simple, yet powerful, connection to most microprocessor, often without additional logic.

The device includes a 128 bit Protection Register. The Protection Register is divided into two 64 bit segments, the first one is written by the manufacturer (contact STMicroelectronics to define the code to be written here), while the second one is programmable by the user. The user programmable segment can be locked.

The memory is available in TSOP56 (14 x 20 mm) and TBGA64 (10x13mm, 1mm pitch) packages.