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Description: The M68Z512W is a 4Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device fe...


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M68Z512W General Description


The M68Z512W is a 4Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal ad- dress access and cycle times. It requires a single 3V ±10% supply, and all inputs and outputs are TTL compatible.

This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected.

The M68Z512W is available in a 32-lead TSOP II (10 x 20mm) package.

M68Z512W Maximum Ratings

Symbol Parameter Value Unit
TA Ambient Operating Temperature 0 to 70
TSTG(1) Storage Temperature 65 to 150
VIO(2) Input or Output Voltage 0.3 to VCC + 0.3 V
VCC Supply Voltage 0.3 to 4.6 V
IO(3) Output Current 20 mA
PD Power Dissipation 1 W

Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 and 120 seconds).
2. Up to a maximum operating VCC of 3.6V only.
3. One output at a time, not to exceed 1 second duration.

M68Z512W Features

` ULTRA LOW DATA RETENTION CURRENT
400nA (typical)
10µA (max)
` OPERATION VOLTAGE: 2.7 TO 3.6V
` 512 Kbit x 8 SRAM WITH OUTPUT ENABLE
` EQUAL CYCLE and ACCESS TIMES: 70ns
` LOW VCC DATA RETENTION: 1V
` TRI-STATE COMMON I/O
` CMOS FOR OPTIMUM SPEED/POWER
` AUTOMATIC POWER-DOWN WHEN DESELECTED
` INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER® SUPERVISORS

M68Z512W Connection Diagram

M68Z512W  Connection Diagram

M68Z512W datasheet

M68Z512W
PDF/DataSheet Download

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