M69AR048B

` SUPPLY VOLTAGE: 1.65 to 1.95V
` ACCESS TIMES: 70ns, 80ns, 85ns
` LOW STANDBY CURRENT: 100µA
` DEEP POWER-DOWN CURRENT: 10µA
` BYTE CONTROL: UB/LB
` PROGRAMMABLE PARTIAL ARRAY
` COMPATIBLE WITH STANDARD LPSRAM
` TRI-STATE COMMON I/O
` 8 WORD PAGE ACCESS CAPABILITY: 25ns
` WIDE OPERATING TEMPERATURE
TA = 30 to +85
` PARTIAL POWER-DOWN MODES
Deep Power-Down
4 Mbit Partial Power-Down
8 Mbit Partial Power-Down
16 Mbit Partial Power-Down

The M69AR048B is a 32 Mbit (33,554,432 bit) CMOS memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 1.65V to 1.95V supply voltage range.

M69AR048B is a member of STMicroelectronics 1T/1C (one transistor per cell) memory family. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area.

However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface.

The internal control logic of the M69AR048B handles the periodic refresh cycle, automatically, and without user involvement.

Write cycles can be performed on a single Byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB).

The device can be put into standby mode using Chip Enable (E1) or in Power-Down mode by using Chip Enable (E2).

The device features several Power-Down modes, making of power saving a user configurable option:
· Partial Power-Down (4 Mbits, 8 Mbits or 16 Mbits) performs a limited refresh of the part of the PSRAM array that contains essential data.
· Deep Power-Down achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh.