M95128 General Description
These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is
organized as 32768 x 8 bit (M95256) and 16384 x 8 bit (M95128).
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figure 2..
The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold HOLD).
M95128 Features
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
Single Supply Voltage:
4.5 to 5.5V for M95xxx
2.5 to 5.5V for M95xxx-W
1.8 to 5.5V for M95xxx-R
High Speed
10MHz Clock Rate, 5ms Write Time
Status Register
Hardware Protection of the Status Register
BYTE and PAGE WRITE (up to 64 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
More than 100000 Erase/Write Cycles
More than 40-Year Data Retention
M95128 Connection Diagram
Map list: ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789All