M95320-W General Description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held
High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 16. to Table 20.).These signals are described nextSerial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives in-structions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, address-es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
M95320-W Features
Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes)
Single Supply Voltage:
4.5 to 5.5V for M95320 and M95640
2.5 to 5.5V for M95320-W and M95320-W
1.8 to 5.5V for M95320-R and M95640-R
1.65 to 5.5V for M95320-S and M95640-S
20MHz, 10MHz, 5MHz or 2MHz clock rates
5ms or 10ms Write Time
Status Register
Hardware Protection of the Status Register
BYTE and PAGE WRITE (up to 32 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
More than 100000 or 1 million Erase/Write Cycles (depending on ordering options)
More than 40-Year Data Retention
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