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Part Number: MA808
Description: The MA808 Frame Aligner chip has been primarily designed for use in equipment operating at the CCITT s...
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MA808
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DataSheet
General Description
MA808 General Description
The MA808 Frame Aligner chip has been primarily designed for use in equipment operating at the CCITT standard of 2048 kbit/s tor 30 channel PCM data signals.
The basic function of the device is to accept a 2048 kbit/s data signal, whose frame structure conforms to CCITT recommendation G732 and frame synchronously align it to a local exchange/system clock.
The frame aligner operation is such that once a synchronisation sequence, as defined in CCITT recommendation G732, is received from a distant source synchronisation is established. Consequently the data stream is delayed such as to align it to the timing required at the local source. Once three successive sync. words are received containing errors, synchronisation is lost. The chip will remain out of sync. until the synchronising sequence is received.
The device can also, when configured in the 'enhanced mode' perform the additional function of time slot zero recovery.
A number of facilities are also provided to simplify the testing of the device and associated system.
MA808 Maximum Ratings
Supply voltage, VDD-VSS ..................- 0.3 to + 7.0V
Voltage on any pin (VIN) (See note 1) ......VSS - 0.3V to VDD + 0.3V
Current through any pin (See note 1) ..............± 20mA
Storage temperature................. -55°C to + 125°C
Operating temperature range ..............-10°C to+55°C
NOTES 1. Guaranteed no latch-up conditions. 2. Stresses above those listed in the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions, or at any other condition above those indicated in the Electrical Characteristics, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
MA808 Features
·Fabricated in Low Power CMOS
·Optional Time Slot Zero Receiver
·Detection of Frame Alignment Signals for 30 Channel PCM Highways Operating at 2048 kbit/s in Accordance with CCITT Recommendations G732
·Delay Compensation and Clock Alignment between the Transmission Line system and the Exchange
·Compensation of Phase Jitter, Meeting the Requirements of CCITT
·Detection and Indication of Loss of Frame Alignment
·Provision of a Signal for Generation of AIS
·Slip Compensation
·Chip Functional Test Facilities
·TTL Compatible
·Operating Power Consumption 75mW max.
·Single + 5V Supply
·High Latch-up Immunity
·256 kHz Clock Output
·Optional Time Slot Zero Receiver
·Detection of Frame Alignment Signals for 30 Channel PCM Highways Operating at 2048 kbit/s in Accordance with CCITT Recommendations G732
·Delay Compensation and Clock Alignment between the Transmission Line system and the Exchange
·Compensation of Phase Jitter, Meeting the Requirements of CCITT
·Detection and Indication of Loss of Frame Alignment
·Provision of a Signal for Generation of AIS
·Slip Compensation
·Chip Functional Test Facilities
·TTL Compatible
·Operating Power Consumption 75mW max.
·Single + 5V Supply
·High Latch-up Immunity
·256 kHz Clock Output
MA808 Typical Application
·Digital Multiplex Equipment
·Interfaces between PCM Line and Switching Systems
·Concentrators
·Interfaces between PCM Line and Switching Systems
·Concentrators
MA808 Connection Diagram
MA808
PDF/DataSheet Download
- Datasheet: MA808
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