Purchase MB90F343/C(S), In-stock MB90F343/C(S) From SeekIC.
Part Number: MB90F343/C(S)
Description: The MB90340-series with up to 2 FULL-CAN* interfaces and FLASH ROM is especially designed for automoti...
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MB90F343/C(S)
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DataSheet
General Description
MB90F343/C(S) General Description
The MB90340-series with up to 2 FULL-CAN* interfaces and FLASH ROM is especially designed for automotive and industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 mm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 512 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free running timers. 4 UARTs constitute additional functionality for communication purposes.
MB90F343/C(S) Features
· Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed. (devices without Ssuffix
only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied
PLL clock).
· 16 Mbyte CPU memory space
• 24-bit internal addressing
· Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes(23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
· Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
· Increased processing speed
• 4-byte instruction queue
· Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
· Automatic data transfer function independent of CPU
• Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
· Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
· Process
• CMOS technology
· I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
· Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
· Full-CAN interface : up to 2 channels
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
· UART (LIN/SCI) : up to 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
· I2C interface* : up to 2 channels (devices with C-suffix only)
• Up to 400 kbit/s transfer rate
· DTP/External interrupt : up to 16 channels, CAN wakeup : up to 2 channels
• Module for activation of expanded intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
· Delay interrupt generator module
• Generates interrupt request for task switching.
· 8/10-bit A/D converter : 16/24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 ms (at 24-MHz machine clock, including sampling time)
· Program patch function
• Address matching detection for 6 address pointers.
· Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
· Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
· ROM security function
• Protects the content of ROM (MASK ROM device only)
· External bus interface
· Clock monitor function
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed. (devices without Ssuffix
only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied
PLL clock).
· 16 Mbyte CPU memory space
• 24-bit internal addressing
· Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes(23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
· Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
· Increased processing speed
• 4-byte instruction queue
· Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
· Automatic data transfer function independent of CPU
• Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
· Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
· Process
• CMOS technology
· I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
· Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
· Full-CAN interface : up to 2 channels
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
· UART (LIN/SCI) : up to 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
· I2C interface* : up to 2 channels (devices with C-suffix only)
• Up to 400 kbit/s transfer rate
· DTP/External interrupt : up to 16 channels, CAN wakeup : up to 2 channels
• Module for activation of expanded intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
· Delay interrupt generator module
• Generates interrupt request for task switching.
· 8/10-bit A/D converter : 16/24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 ms (at 24-MHz machine clock, including sampling time)
· Program patch function
• Address matching detection for 6 address pointers.
· Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
· Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
· ROM security function
• Protects the content of ROM (MASK ROM device only)
· External bus interface
· Clock monitor function
MB90F343/C(S) Connection Diagram
MB90050
PDF/DataSheet Download
- Datasheet: MB90050
- File Size: 760910 KB
- Manufacturer: FUJITSU [Fujitsu Media Devices Limited]
- Click here to Download
- ·MB90050PF
- FUJITSU [Fujitsu Media Devices Limited]
- On-Screen Display Controller
- 760910 KB
- ·MB90075
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90075-PF
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90075-P-SH
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90089-PF
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCREEN DISPLAY CONTROLLER
- 2390199 KB
- ·MB90091
- FUJITSU [Fujitsu Media Devices Limited]
- Intelligent On-screen Display Controller (IOSDC)
- 416577 KB
- ·MB90091A
- FUJITSU [Fujitsu Media Devices Limited]
- Intelligent On-screen Display Controller (IOSDC)
- 416577 KB
- ·MB90091AP
- FUJITSU [Fujitsu Media Devices Limited]
- Intelligent On-screen Display Controller (IOSDC)
- 416577 KB
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