Purchase MBM29DL32TF/BF, In-stock MBM29DL32TF/BF From SeekIC.
Part Number: MBM29DL32TF/BF
Description: The MBM29DL32TF/BF are a 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 ...
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MBM29DL32TF/BF
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DataSheet
General Description
MBM29DL32TF/BF General Description
The MBM29DL32TF/BF are a 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL32TF/BF Maximum Ratings
| Parameter |
Conditions |
Rating |
Units | |
|
Min |
Max | |||
| Storage Temperature |
Tstg |
55 |
+125 |
°C |
| Ambient Temperature with Power Applied |
TA |
40 |
+85 |
°C |
| Voltage with Respect to Ground All Pins except A9, OE, RESET *1, *2 |
VIN, VOUT |
0.5 |
VCC+0.5 |
V |
| Power Supply Voltage *1 |
VCC |
0.5 |
+4.0 |
V |
| A9, OE, and RESET *1, *3 |
VIN |
0.5 |
+13.0 |
V |
| WP/ACC *1, *4 |
VACC |
0.5 |
+10.5 |
V |
MBM29DL32TF/BF Features
• 0.17 mm Process Technology
• Two-bank Architecture for Simultaneous Read/Program and Read/Erase
• FlexBankTM
-Bank A : 4 Mbit (8 KB ´ 8 and 64 KB ´ 7)
-Bank B : 12 Mbit (64 KB ´ 24)
-Bank C : 12 Mbit (64 KB ´ 24)
-Bank D : 4 Mbit (64 KB ´ 8)
-Two virtual Banks are chosen from the combination of four physical banks (Refer to "FlexBankTM Architecture
-Table" and "Example of Virtual Banks Combination Table" in nFUNCTIONAL DESCRIPTION)
-Host system can program or erase in one bank, and then read immediately and simultaneously from the other
-bank with zero latency between read and write operations.
-Read-while-erase
-Read-while-program
• Single 3.0 V Read, Program, and Erase Minimizes system level power requirements
• Compatible with JEDEC-standard Commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard World-wide Pinouts
-48-pin TSOP (1) (Package suffix : TN - Normal Bend Type)
-48-ball FBGA (Package suffix : PBT)
• Low VCC write inhibit £ 2.5 V
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same
• Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
• Minimum 100,000 Program/Erase Cycles
• High Performance 70 ns maximum access time
• Sector Erase Architecture
-Eight 4 K word and sixty-three 32 K word sectors in word mode
-Eight 8 K byte and sixty-three 64 K byte sectors in byte mode
-Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture T = Top sector B = Bottom sector
• HiddenROM Region 256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin At VIL, allows protection of "outermost" 2 ´ 8 bytes on boot sectors, regardless of sector group protection/ unprotection status. At VACC, increases program performance
• Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
• Two-bank Architecture for Simultaneous Read/Program and Read/Erase
• FlexBankTM
-Bank A : 4 Mbit (8 KB ´ 8 and 64 KB ´ 7)
-Bank B : 12 Mbit (64 KB ´ 24)
-Bank C : 12 Mbit (64 KB ´ 24)
-Bank D : 4 Mbit (64 KB ´ 8)
-Two virtual Banks are chosen from the combination of four physical banks (Refer to "FlexBankTM Architecture
-Table" and "Example of Virtual Banks Combination Table" in nFUNCTIONAL DESCRIPTION)
-Host system can program or erase in one bank, and then read immediately and simultaneously from the other
-bank with zero latency between read and write operations.
-Read-while-erase
-Read-while-program
• Single 3.0 V Read, Program, and Erase Minimizes system level power requirements
• Compatible with JEDEC-standard Commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard World-wide Pinouts
-48-pin TSOP (1) (Package suffix : TN - Normal Bend Type)
-48-ball FBGA (Package suffix : PBT)
• Low VCC write inhibit £ 2.5 V
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same
• Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
• Minimum 100,000 Program/Erase Cycles
• High Performance 70 ns maximum access time
• Sector Erase Architecture
-Eight 4 K word and sixty-three 32 K word sectors in word mode
-Eight 8 K byte and sixty-three 64 K byte sectors in byte mode
-Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture T = Top sector B = Bottom sector
• HiddenROM Region 256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin At VIL, allows protection of "outermost" 2 ´ 8 bytes on boot sectors, regardless of sector group protection/ unprotection status. At VACC, increases program performance
• Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
MBM100A6
PDF/DataSheet Download
- Datasheet: MBM100A6
- File Size: 79491 KB
- Manufacturer: HITACHI [Hitachi Semiconductor]
- Click here to Download
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MBM29DL32TF/BF Relative Products
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The MBM29DL16XTE/BE70 are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-ball FBGA Package. These devices are designed to be programmed in-system...
MBM29DL16XTE
The MBM29DL16XTE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.These devices are designed to be programmed in-system with ...
MBM29DL16XTD/BD
The MBM29DL16XTD/BD is a 32M-bit, 5.0 V-Only Flash memory organized as 4M bytes of 8 bits each. The 2M bytes of data is divided into 64 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ0 to DQ7. The MBM29DL16XTD/BD is of...
MBM29DL16XTD
The MBM29DL16XTD/BD are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.These devices are designed to be programmed in-system wi...
MBM29DL16XBE
The MBM29DL16XBE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.These devices are designed to be programmed in-system with ...
MBM29DL16XBD
The MBM29DL16XTD/BD are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.These devices are designed to be programmed in-system wi...
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