MBM29DL400TC

The MBM29DL400TC/BC are a 4M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each or256K words of 16 bits each. The MBM29DL400TC/BC are offered in a 48-pin TSOP(I)  package. These devicesare designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPPand 5.0 V VCCare not required for write or erase operations. The devices can also be reprogrammed in standard EPROMprogrammers.

MBM29DL400TC/BC provides simultaneous operation which can read a data while program/erase. Thesimultaneous operation architecture provides simultaneous operation by dividing the memory space into twobanks. The device can allow a host system to program or erase in one bank, then immediately and simultaneously read from the other bank.

The standard MBM29DL400TC/BC offer access times 55 ns and 120 ns, allowing operation of high-speedmicroprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),write enable (WE), and output enable (OE) controls.

The MBM29DL400TC/BC are pin and command set compatible with JEDEC standard E2PROMs. Commandsare written to the command register using standard microprocessor write timings. Register contents serve asinput to an internal state-machine which controls the erase and programming circuitry. Write cycles also internallylatch addresses and data needed for the programming and erase operations. Reading data out of the devicesis similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29DL400TC/BC are programmed by executing the program command sequence. This will invoke theEmbedded Program Algorithm which is an internal algorithm that automatically times the program pulse widthsand verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmedbefore executing the erase operation. During erase, the devices automatically time the erase pulse widths andverify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased andreprogrammed without affecting other sectors. The MBM29DL400TC/BC are erased when shipped from thefactory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generatedand regulated voltages are provided for the program and erase operations. A low VCC detector automaticallyinhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has beencompleted, the devices internally reset to the read mode.

Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levelsof quality, reliability, and cost effectiveness. The MBM29DL400TC/BC memories electrically erase the entire chipor all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed onebyte/word at a time using the EPROM programming mechanism of hot electron injection