Purchase MBM29DL64DF-70, In-stock MBM29DL64DF-70 From SeekIC.
MFG:FUJ
Part Number: MBM29DL64DF-70
MFG: FUJ
Description: MBM29DL64DF is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 M words o...
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MBM29DL64DF-70
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DataSheet
General Description
MBM29DL64DF-70 General Description
MBM29DL64DF is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 M words of 16 bits each. The device comes in 48-pin TSOP (1) and 48-ball FBGA packages. This device is designed to be programmed in system with 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations.
The device can also be reprogrammed in standard EPROM programmers. The device is organized into four physical banks : Bank A, Bank B, Bank C and Bank D, which are considered to be four separate memory arrays operations. This device is the almost identical to Fujitsu's standard 3 V only Flash memories, with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.
MBM29DL64DF-70 Maximum Ratings
| Parameter |
Conditions |
Rating |
Units | |
|
Min |
Max | |||
| Storage Temperature |
Tstg |
55 |
+125 |
°C |
| Ambient Temperature with Power Applied |
TA |
40 |
+85 |
°C |
| Voltage with Respect to Ground All Pins except A9, OE, RESET *1, *2 |
VIN, VOUT |
0.5 |
VCC+0.5 |
V |
| Power Supply Voltage *1 |
VCC |
0.5 |
+4.0 |
V |
| A9, OE, and RESET *1, *3 |
VIN |
0.5 |
+13.0 |
V |
| WP/ACC *1, *4 |
VACC |
0.5 |
+10.5 |
V |
MBM29DL64DF-70 Features
• 0.17 mm Process Technology
• Two-bank Architecture for Simultaneous Read/Program and Read/Erase
• FlexBankTM *1
-Bank A : 8 Mbit (8 KB ´ 8 and 64 KB ´ 15)
-Bank B : 24 Mbit (64 KB ´ 48)
-Bank C : 24 Mbit (64 KB ´ 48)
-Bank D : 8 Mbit (8 KB ´ 8 and 64 KB ´ 15)
-Two virtual Banks are chosen from the combination of four physical banks (Refer to "nFUNCTIONAL
-DESCRIPTION FlexBankTM Architecture"and "Example of Virtual Banks Combination".)
-Host system can program or erase in one bank, and then read immediately and simultaneously from the other
-bank with zero latency between read and write operations.
-Read-while-erase
-Read-while-program
• Single 3.0 V Read, Program, and Erase Minimized system level power requirements
• Compatible with JEDEC-standard Commands Uses the same software commands as E2PROMs
• Compatible with JEDEC-standard Worldwide Pinouts
-48-pin TSOP (1) (Package suffix : TN - Normal Bend Type)
-48-ball FBGA (Package suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• High Performance 70 ns maximum access time
• Sector Erase Architecture
-Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode
-Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• HiddenROM Region
-256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
-Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
-At VIL allows protection of "outermost" 2 ´ 8 Kbytes on both ends of boot sectors, regardless of sector group
-protection/unprotection status
At VACC, increases program performance
• Embedded EraseTM *2 Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms
-Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit fea ture for program detection or erase cycle completion
• Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCC Write Inhibit £ 2.5 V
• Program Suspend/Resume Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector Group Protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
• Two-bank Architecture for Simultaneous Read/Program and Read/Erase
• FlexBankTM *1
-Bank A : 8 Mbit (8 KB ´ 8 and 64 KB ´ 15)
-Bank B : 24 Mbit (64 KB ´ 48)
-Bank C : 24 Mbit (64 KB ´ 48)
-Bank D : 8 Mbit (8 KB ´ 8 and 64 KB ´ 15)
-Two virtual Banks are chosen from the combination of four physical banks (Refer to "nFUNCTIONAL
-DESCRIPTION FlexBankTM Architecture"and "Example of Virtual Banks Combination".)
-Host system can program or erase in one bank, and then read immediately and simultaneously from the other
-bank with zero latency between read and write operations.
-Read-while-erase
-Read-while-program
• Single 3.0 V Read, Program, and Erase Minimized system level power requirements
• Compatible with JEDEC-standard Commands Uses the same software commands as E2PROMs
• Compatible with JEDEC-standard Worldwide Pinouts
-48-pin TSOP (1) (Package suffix : TN - Normal Bend Type)
-48-ball FBGA (Package suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• High Performance 70 ns maximum access time
• Sector Erase Architecture
-Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode
-Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• HiddenROM Region
-256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
-Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
-At VIL allows protection of "outermost" 2 ´ 8 Kbytes on both ends of boot sectors, regardless of sector group
-protection/unprotection status
At VACC, increases program performance
• Embedded EraseTM *2 Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms
-Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit fea ture for program detection or erase cycle completion
• Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCC Write Inhibit £ 2.5 V
• Program Suspend/Resume Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector Group Protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
MBM29DL64DF-70 Connection Diagram
MBM29DL64DF-70
PDF/DataSheet Download
- Datasheet: MBM29DL64DF-70
- File Size: 875052 KB
- Manufacturer: FUJITSU [Fujitsu Media Devices Limited]
- Click here to Download
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