Purchase MC-45D16CB641, In-stock MC-45D16CB641 From SeekIC.
Part Number: MC-45D16CB641
Description: The MC-45D16CB641 is a 16,777,216 words by 64 bits DDR synchronous dynamic RAM module on which 8 pie...
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MC-45D16CB641
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General Description
MC-45D16CB641 General Description
The MC-45D16CB641 is a 16,777,216 words by 64 bits DDR synchronous dynamic RAM module on which 8 pieces of 128M DDR SDRAM: µPD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
MC-45D16CB641 Maximum Ratings
| Parameter | Symbol | Condition | Rating | Unit |
| Voltage on power supply pin relative to VSS | VDD, VDDQ | 0.5 to +3.6 | V | |
| Voltage on input pin relative to GND | VT | 0.5 to +3.6 | V | |
| Short circuit output current | IO | 50 | mA | |
| Power dissipation | PD | 12 | W | |
| Storage temperature | Tstg | 55 to +125 |
MC-45D16CB641 Features
• 16,777,216 words by 64 bits organization
• Clock frequency
• Fully Synchronous Dynamic RAM with all signals except DM,DQS,DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• 2.5 V ± 0.2 V Power supply for VDD
• 2.5 V ± 0.2 V Power supply for VDDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
• Clock frequency
• Fully Synchronous Dynamic RAM with all signals except DM,DQS,DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• 2.5 V ± 0.2 V Power supply for VDD
• 2.5 V ± 0.2 V Power supply for VDDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
MC-45D16CB641 Connection Diagram
MC-45D16CB641
PDF/DataSheet Download
- Datasheet: MC-45D16CB641
- File Size: 250371 KB
- Manufacturer: NEC [NEC]
- Click here to Download
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