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Part Number: MC-45D32CD641
Description: The MC-45D32CD641 is a 33,554,432 words by 64 bits DDR synchronous dynamic RAM module on which 16 piec...
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MC-45D32CD641
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General Description
MC-45D32CD641 General Description
The MC-45D32CD641 is a 33,554,432 words by 64 bits DDR synchronous dynamic RAM module on which 16 pieces of 128M DDR SDRAM: PD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
MC-45D32CD641 Maximum Ratings
| Parameter | Symbol | Condition | Rating | Unit |
| Voltage on power supply pin relative to VSS | VCC | 0.5 to +4.6 | V | |
| Voltage on input pin relative to VSS | VT | 0.5 to +4.6 | V | |
| Short circuit output current | IO | 50 | mA | |
| Power dissipation | PD | 12 | W | |
| Storage temperature | Tstg | 55 to +125 | °C |
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
MC-45D32CD641 Features
· 33,554,432 words by 64 bits organization
· Clock frequency
· Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge
· Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
· Quad internal banks operation
· Possible to assert random column address in every clock cycle
· Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
· Automatic precharge and controlled precharge
· CBR (Auto) refresh and self refresh
· 2.5 V ± 0.2 V Power supply for VDD
· 2.5 V ± 0.2 V Power supply for VDDQ
· SSTL_2 compatible with all signals
· 4,096 refresh cycles / 64 ms
· Burst termination by Precharge command and Burst stop command
· 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
· Unbuffered type
· Serial PD
· Clock frequency
| Part number | /CAS latency | Clock frequency (MAX.) | Module type |
| MC-45D32CD641KFA-C75 | CL = 2.5 | 133MHz | DDR SDRAM |
| CL = 2 | 100MHz | Unbuffered DIMM | |
| MC-45D32CD641KFA-C80 | CL = 2.5 | 125 MHz | Design specification |
| CL = 2 | 100 MHz | Rev.0.9 compliant |
· Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
· Quad internal banks operation
· Possible to assert random column address in every clock cycle
· Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
· Automatic precharge and controlled precharge
· CBR (Auto) refresh and self refresh
· 2.5 V ± 0.2 V Power supply for VDD
· 2.5 V ± 0.2 V Power supply for VDDQ
· SSTL_2 compatible with all signals
· 4,096 refresh cycles / 64 ms
· Burst termination by Precharge command and Burst stop command
· 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
· Unbuffered type
· Serial PD
MC-45D32CD641 Connection Diagram
MC-45D32CD641
PDF/DataSheet Download
- Datasheet: MC-45D32CD641
- File Size: 256093 KB
- Manufacturer: NEC [NEC]
- Click here to Download
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