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Part Number: MC3S12RG128
Description: The MC3S12RG128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals...
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MC3S12RG128
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DataSheet
General Description
MC3S12RG128 General Description
The MC3S12RG128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of ROM, 8K bytes of RAM, two asynchronous serial communications interfaces (SCI), two serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two 8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM), and up to two CAN 2.0 A, B software compatible modules (MSCAN12). There is no integrated EEPROM on the MC3S12RG128. The MC3S12RG128 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.
MC3S12RG128 Maximum Ratings
| Num | Rating | Symbol | Min | Max | Unit |
| 1 | I/O, Regulator and Analog Supply Voltage | VDD35 | −0.3 | 6.5 | V |
| 2 | Internal Logic Supply Voltage 2 | VDD | −0.3 | 3.0 | V |
| 3 | PLL Supply Voltage 2 | VDDPLL | −0.3 | 3.0 | V |
| 4 | Voltage difference VDDX to VDDR and VDDA | VDDX | −0.3 | 0.3 | V |
| 5 | Voltage difference VSSX to VSSR and VSSA | VSSX | −0.3 | 0.3 | V |
| 6 | Digital I/O Input Voltage | VIN | −0.3 | 6.5 | V |
| 7 | Analog Reference | VRH, VRL | −0.3 | 6.5 | V |
| 8 | XFC, EXTAL, XTAL inputs | VILV | −0.3 | 3.0 | V |
| 9 | TEST input (for test purposes only, tie to VSS) | VTEST | −0.3 | 6.5 | V |
| 10 | Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 |
ID | −25 | 25 | mA |
| 11 | Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 |
IDL | −25 | 25 | mA |
| 15 | Storage Temperature Range | Tstg | 65 | 155 | °C |
MC3S12RG128 Features
• HCS12 Core
- 16-bit HCS12 CPU
Upward compatible with M68HC11 instruction set
Interrupt stacking and programmer's model identical to M68HC11
20-bit ALU
Instruction queue
Enhanced indexed addressing
- MEBI (Multiplexed External Bus Interface)
- MMC (Module Mapping Control)
- INT (Interrupt control)
- BKP (Breakpoints)
- BDM (Background Debug Module)
• CRG (Clock and Reset Generator)
- Choice of low current Colpitts oscillator or standard Pierce oscillator
- PLL
- COP watchdog
- Real time interrupt
- Clock monitor
• 8-bit and 4-bit ports with interrupt functionality
- Digital filtering
- Programmable rising and falling edge trigger
• Memory Options:
- 128K Byte or 64K Byte ROM
- 8K Byte RAM
• Two 8-channel Analog-to-Digital Converters
- 10-bit resolution
- External conversion trigger capability
• Two 1M bit per second, CAN 2.0 A, B software compatible modules
- Five receive and three transmit buffers
- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
- Four separate interrupt channels for Rx, Tx, error and wake-up
- Low-pass filter wake-up function
- Loop-back for self test operation
• Enhanced Capture Timer
- 16-bit main counter with 7-bit prescaler
- 8 programmable input capture or output compare channels
- Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
- Programmable period and duty cycle
- 8-bit 8-channel or 16-bit 4-channel
- Separate control for each pulse width and duty cycle
- Center-aligned or left-aligned outputs
- Programmable clock select logic with a wide range of frequencies
- Fast emergency shutdown input
- Usable as interrupt inputs
• Serial interfaces
- Two asynchronous Serial Communications Interfaces (SCI)
- Two Synchronous Serial Peripheral Interface (SPI)
• Inter-IC Bus (IIC)
- Compatible with I2C Bus standard
- Multi-master operation
- Software programmable for one of 256 different serial clock frequencies
• Internal 2.5V Regulator
- Supports an input voltage range from 2.97V to 5.5V
- Low power mode capability
- Includes low voltage reset (LVR) circuitry
- Includes low voltage interrupt (LVI) circuitry
• 112-Pin LQFP and 80-Pin QFP package options
- I/O lines with 5V input and drive capability- 5V A/D converter inputs
- Operation at 66 MHz equivalent to 33 MHz Bus Speed (single-chip modes only)
- Operation at 50 MHz equivalent to 25 MHz Bus Speed (expanded modes)
• Development support
- Single-wire background debug™ mode (BDM)
- On-chip hardware breakpoints
- 16-bit HCS12 CPU
Upward compatible with M68HC11 instruction set
Interrupt stacking and programmer's model identical to M68HC11
20-bit ALU
Instruction queue
Enhanced indexed addressing
- MEBI (Multiplexed External Bus Interface)
- MMC (Module Mapping Control)
- INT (Interrupt control)
- BKP (Breakpoints)
- BDM (Background Debug Module)
• CRG (Clock and Reset Generator)
- Choice of low current Colpitts oscillator or standard Pierce oscillator
- PLL
- COP watchdog
- Real time interrupt
- Clock monitor
• 8-bit and 4-bit ports with interrupt functionality
- Digital filtering
- Programmable rising and falling edge trigger
• Memory Options:
- 128K Byte or 64K Byte ROM
- 8K Byte RAM
• Two 8-channel Analog-to-Digital Converters
- 10-bit resolution
- External conversion trigger capability
• Two 1M bit per second, CAN 2.0 A, B software compatible modules
- Five receive and three transmit buffers
- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
- Four separate interrupt channels for Rx, Tx, error and wake-up
- Low-pass filter wake-up function
- Loop-back for self test operation
• Enhanced Capture Timer
- 16-bit main counter with 7-bit prescaler
- 8 programmable input capture or output compare channels
- Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
- Programmable period and duty cycle
- 8-bit 8-channel or 16-bit 4-channel
- Separate control for each pulse width and duty cycle
- Center-aligned or left-aligned outputs
- Programmable clock select logic with a wide range of frequencies
- Fast emergency shutdown input
- Usable as interrupt inputs
• Serial interfaces
- Two asynchronous Serial Communications Interfaces (SCI)
- Two Synchronous Serial Peripheral Interface (SPI)
• Inter-IC Bus (IIC)
- Compatible with I2C Bus standard
- Multi-master operation
- Software programmable for one of 256 different serial clock frequencies
• Internal 2.5V Regulator
- Supports an input voltage range from 2.97V to 5.5V
- Low power mode capability
- Includes low voltage reset (LVR) circuitry
- Includes low voltage interrupt (LVI) circuitry
• 112-Pin LQFP and 80-Pin QFP package options
- I/O lines with 5V input and drive capability- 5V A/D converter inputs
- Operation at 66 MHz equivalent to 33 MHz Bus Speed (single-chip modes only)
- Operation at 50 MHz equivalent to 25 MHz Bus Speed (expanded modes)
• Development support
- Single-wire background debug™ mode (BDM)
- On-chip hardware breakpoints
MC3S12RG128 Connection Diagram
MC3S12RG128
PDF/DataSheet Download
- Datasheet: MC3S12RG128
- File Size: 2055107 KB
- Manufacturer: FREESCALE
- Click here to Download
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