MC54HC563

Features:

* Output Drive Capability: 15 LSTTL Loads
* Outputs Directly Interface to CMOS, NMOS, and TTL
* Operating Voltage Range: 2 to 6 V
* Low Input Current: 1 A
* High Noise Immunity Characteristic of CMOS Devices
* In Compliance with the Requirements Defined by JEDEC Standard No. 7A
* Chip Complexity: 202 FETs or 50.5 Equivalent Gates


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)	1.5 to VCC + 1.5	V
Vout	DC Output Voltage (Referenced to GND)	0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin	±20	mA
Iout	DC Output Current, per Pin	±35	mA
ICC	DC Supply Current, VCC and GND Pins	±75	mA
PD	Power Dissipation in Still Air,Plastic or Ceramic DIP+ SOIC Package+	750 500	mW
Tstg	torage Temperature	65 to + 150	oC
TL	Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)(Ceramic DIP)	260 300	oC

Description

The MC54/74HC563 is identical in pinout to the LS563. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

MC54/74HC563 is identical in function to the HC533 but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board ayout.

These latches of MC54/74HC563 appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears at the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable of MC54/74HC563 input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state.

Thus, data may be latched even when the outputs are not enabled.

The HC573 is the noninverting version of this function.