MFG:MOTOROLA Package Cooled:SOP-20 D/C:1997
MFG: MOTOROLA
Package Cooled: SOP-20
D/C: 1997
Description: The MC74AC540/74ACT540 and MC74AC541/74ACT541 are octal buffer/line drivers designed to be employed as...
The MC74AC540/74ACT540 and MC74AC541/74ACT541 are octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. The MC74AC541/74ACT541 is a noninverting option of the MC74AC540/74ACT540.
These devices are similar in function to the MC74AC240/74ACT240 and MC74AC244/74ACT244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater PC board density.
|
Symbol |
Parameter |
Value |
Unit |
|
VCC |
DC Supply Voltage (Referenced to GND) |
0.5 to +7.0 |
V |
|
Vin |
DC Input Voltage (Referenced to GND) |
0.5 to VCC +0.5 |
V |
|
Vout |
DC Output Voltage (Referenced to GND) |
0.5 to VCC +0.5 |
V |
|
Iin |
DC Input Current, per Pin |
±20 |
mA |
|
Iout |
DC Output Sink/Source Current, per Pin |
±50 |
mA |
|
ICC |
DC VCC or GND Current per Output Pin |
±50 |
mA |
|
Tstg |
Storage Temperature |
65 to +150 |
MC74AC541
PDF/DataSheet Download
IC BUFFER/LINEDRVR OCTAL 20-DIP
IC BUFFER/LINEDRVR OCTAL 20-SOIC
IC BUFFER/LINEDRVR OCTAL 20-SOIC
The MC74AC540/74ACT540 and MC74AC541/74ACT541 are octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. The MC74AC541/74ACT541 is a noninverting option of the MC74AC540/74ACT540...
The MC74AC534/74ACT534 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip flops MC74AC53...
The MC74AC533/74ACT533 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops MC74AC533 appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched...
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